SH7055S Datasheet, PDF (129/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

The exception flag bits in the FPSCR are always updated, regardless of whether or not an FPU
exception is accepted, and remain set until the user clears them explicitly with an instruction.
FPSCR cause bits change each time an FPU instruction is executed.
Exception events other than those defined in the IEEE754 standard (i.e., underflow, overflow, and
inexact exceptions) are detected by the FPU but do not result in the generation of any kind of
exception. Neither is an FPU exception generated by a floating-point instruction relating to data
transfer, such as FLOAT.
6.6 When Exception Sources Are Not Accepted
When an address error or interrupt is generated after a delayed branch instruction or interrupt-
disabled instruction, it is sometimes not accepted immediately but stored instead, as shown in
table 6.10. When this happens, it will be accepted when an instruction that can accept the
exception is decoded.
Table 6.10 Generation of Exception Sources Immediately after a Delayed Branch
Instruction or Interrupt-Disabled Instruction
Exception Source
Point of Occurrence
Bus Error
Interrupt
FPU Exception
Immediately after a delayed branch
instruction^*1
Not accepted
Not accepted Not accepted
Immediately after an interrupt-disabled
instruction^*2
Not accepted^*4 Not accepted Accepted
Immediately after an FPU instruction^*3 Not accepted
Not accepted Accepted
Notes: *1. Delayed branch instructions: JMP, JSR, BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
*2. Interrupt-disabled instructions: LDC, LDC.L, STC, STC.L, LDS, LDS.L, STS, STS.L
*3. FPU instructions: Table 2.18, Floating-Point Instructions, and table 2.19, FPU-Related
CPU Instructions, in section 2.4.1, Instruction Set by Classification.
*4. In the SH-2 a bus error is accepted.
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