SH7055S Datasheet, PDF (295/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bits 7 to 1—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 0—Compare-Match Flag 1 (CMF1): Status flag that indicates OCR1 compare-match.
Bit 0: CMF1
0
1
Description
[Clearing condition]
When CMF1 is read while set to 1, then 0 is written to CMF1
[Setting condition]
When TCNT1B = OCR1
(Initial value)
Timer Status Registers 2A and 2B (TSR2A, TSR2B)
TSR2A: TSR2A indicates the status of channel 2 input capture, compare-match, and overflow.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVF2A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Bit:
Initial value:
R/W:
7
IMF2H
0
R/(W)*
6
IMF2G
0
R/(W)*
5
IMF2F
0
R/(W)*
4
IMF2E
0
R/(W)*
3
IMF2D
0
R/(W)*
2
IMF2C
0
R/(W)*
1
IMF2B
0
R/(W)*
0
IMF2A
0
R/(W)*
Note: * Only 0 can be written to clear the flag.
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 2A (OVF2A): Status flag that indicates TCNT2A overflow.
Bit 8: OVF2A
0
1
Description
[Clearing condition]
(Initial value)
When OVF2A is read while set to 1, then 0 is written to OVF2A
[Setting condition]
When the TCNT2A value overflows (from H'FFFF to H'0000)
Rev.2.0, 07/03, page 257 of 960