SH7055S Datasheet, PDF (662/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.3.3 Data Register (SDDR)
The data register (SDDR) comprises data register H (SDDRH) and data register L (SDDRL), each
of which has the following configuration.
Bit: 15
14
13
12
11
10
9
8
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
Initial value: —
—
—
—
—
—
—
—
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
SDDRH and SDDRL are 16-bit registers that can be read and written to by the CPU. SDDR is
connected to TDO and TDI for serial data transfer to and from an external device.
32-bit data is input and output in serial data transfer. If data exceeding 32 bits is input, only the
last 32 bits will be stored in SDDR. Serial data is input starting with the MSB of SDDR (bit 15 of
SDDRH), and output starting with the LSB (bit 0 of SDDRL).
SDDR is not initialized by a reset, in hardware or software standby mode, or by the TRST signal.
18.3.4 Bypass Register (SDBPR)
The bypass register (SDBPR) is a one-bit shift register. In bypass mode, SDBPR is connected to
TDI and TDO, and the SH7055SF chip is bypassed in a board test. SDBPR cannot be read or
written to by the CPU.
Rev.2.0, 07/03, page 624 of 960