SH7055S Datasheet, PDF (119/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

When exception processing starts, the CPU operates as follows:
1. Exception processing triggered by reset:
The initial values of the program counter (PC) and stack pointer (SP) are fetched from the
exception processing vector table (PC and SP are respectively the H'00000000 and
H'00000004 addresses for power-on resets and the H'00000008 and H'0000000C addresses for
manual resets). See section 6.1.3, Exception Processing Vector Table, for more information.
H'00000000 is then written to the vector base register (VBR) and H'F (1111) is written to the
interrupt mask bits (I3–I0) of the status register (SR). The program begins running from the PC
address fetched from the exception processing vector table.
2. Exception processing triggered by address errors, interrupts and instructions:
SR and PC are saved to the stack indicated by R15. For interrupt exception processing, the
interrupt priority level is written to the SR’s interrupt mask bits (I3–I0). For address error and
instruction exception processing, the I3–I0 bits are not affected. The start address is then
fetched from the exception processing vector table and the program begins running from that
address.
6.1.3 Exception Processing Vector Table
Before exception processing begins running, the exception processing vector table must be set in
memory. The exception processing vector table stores the start addresses of exception service
routines. (The reset exception processing table holds the initial values of PC and SP.)
All exception sources are given different vector numbers and vector table address offsets, from
which the vector table addresses are calculated. During exception processing, the start addresses of
the exception service routines are fetched from the exception processing vector table, which is
indicated by this vector table address.
Table 6.3 shows the vector numbers and vector table address offsets. Table 6.4 shows how vector
table addresses are calculated.
Table 6.3 Exception Processing Vector Table
Exception Sources
Power-on reset
PC
SP
Manual reset
PC
SP
General illegal instruction
(Reserved by system)
Vector
Numbers
0
1
2
3
4
5
Vector Table Address†Offset
H'00000000–H'00000003
H'00000004–H'00000007
H'00000008–H'0000000B
H'0000000C–H'0000000F
H'00000010–H'00000013
H'00000014–H'00000017
Rev.2.0, 07/03, page 81 of 960