SH7055S Datasheet, PDF (227/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

10.5 Usage Notes
1. Only word (16-bit) access can be used on the DMA operation register (DMAOR). All other
registers can be accessed in word (16-bit) or longword (32-bit) units.
2. When rewriting the RS0–RS4 bits of CHCR0–CHCR3, first clear the DE bit to 0 (clear the DE
bit to 0 before modifying CHCR).
3. When an NMI interrupt is input, the NMIF bit of DMAOR is set even when the DMAC is not
operating.
4. Clear the DME bit of DMAOR to 0 and make certain that any transfer request processing
accepted by the DMAC has been completed before entering standby mode.
5. Do not access the DMAC, BSC, or UBC on-chip peripheral modules from the DMAC.
6. When activating the DMAC, make the CHCR settings as the final step. Abnormal operation
may result if any other registers are set last.
7. After the DMATCR count becomes 0 and the DMA transfer ends normally, always write 0 to
DMATCR, even when executing the maximum number of transfers on the same channel.
Abnormal operation may result if this is not done.
8. Designate burst mode as the transfer mode when using the address reload function. Abnormal
operation may result in cycle-steal mode.
9. Designate a multiple of four for the DMATCR value when using the address reload function,
otherwise abnormal operation may result.
10. Do not access empty DMAC register addresses. Operation cannot be guaranteed when empty
addresses are accessed.
11. If DMAC transfer is aborted by NMIF or AE setting, or DME or DE clearing, during DMAC
execution with address reload on, the SAR2, DAR2, and DMATCR2 settings should be made
before re-executing the transfer. The DMAC may not operate correctly if this is not done.
12. Do not set the DE bit to 1 while bits RS0 to RS4 in CHCR0 to CHCR3 are still set to “no
request.”
Rev.2.0, 07/03, page 189 of 960