SH7055S Datasheet, PDF (672/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Pin Functions in Branch Trace Mode
Pin
AUDCK
AUDSYNC
AUDATA3 to
AUDATA0
Description
This pin outputs 1/2 the operating frequency (φ/2).
This is the clock for AUDATA synchronization.
This pin indicates whether output from AUDATA is valid.
High: Valid data is not being output
Low: An address is being output
1. When AUDSYNC is low
When a program branch or interrupt branch occurs, the AUD asserts
AUDSYNC and outputs the branch destination address. The output order is
A3–A0, A7–A4, A11–A8, A15–A12, A19–A16, A23–A20, A27–A24, A31–A28.
2. When AUDSYNC is high
When waiting for branch destination address output, these pins constantly
output 0011.
When an branch occurs, AUDATA3–AUDATA2 output 10, and AUDATA1–
AUDATA0 indicate whether a 4-, 8-, 16-, or 32-bit address is to be output by
comparing the previous fully output address with the address output this time
(see table below).
AUDATA1, AUDATA0
00 Address bits A31–A4 match; 4 address bits A3–A0 are to be
output (i.e. output is performed once).
01 Address bits A31–A8 match; 8 address bits A3–A0 and A7–A4
are to be output (i.e. output is performed twice).
10 Address bits A31–A16 match; 16 address bits A3–A0, A7–A4,
A11–A8, and A15–A12 are to be output (i.e. output is
performed four times).
11 None of the above cases applies; 31 address bits A3–A0, A7–
A4, A11–A8, and A15–A12, A19–A16, A23–A20, A27–A24,
and
A31–A28 are to be output (i.e. output is performed eight
times).
Rev.2.0, 07/03, page 634 of 960