SH7055S Datasheet, PDF (658/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 18.3 Serial Transfer Characteristics of H-UDI Registers
Register
SDIR
SDSR
SDDRH
SDDRL
SDBPR
Serial Input
Possible
Not possible
Possible
Possible
Possible
Serial Output
Possible
Possible
Possible
Possible
Possible
18.2 External Signals
18.2.1 Test Clock (TCK)
The test clock pin (TCK) supplies an independent clock to the H-UDI. As the clock input to TCK
is supplied directly to the H-UDI, a clock waveform with a duty ratio close to 50% should be input
(see section 25, Electrical Characteristics, for details). If no signal is input, TCK is fixed at 1 by
internal pull-up.
18.2.2 Test Mode Select (TMS)
The test mode select pin (TMS) is sampled at the rise of TCK. TMS controls the internal status of
the TAP controller. If no signal is input, TMS is fixed at 1 by internal pull-up.
18.2.3 Test Data Input (TDI)
The test data input pin (TDI) performs serial input of instructions and data to H-UDI registers.
TDI is sampled at the rise of TCK. If no signal is input, TDI is fixed at 1 by internal pull-up.
18.2.4 Test Data Output (TDO)
The test data input pin (TDO) performs serial output of instructions and data from H-UDI
registers. Transfer is synchronized with TCK. When no signal is being output, TDO goes to the
high-impedance state.
18.2.5 Test Reset (TRST)
The test reset pin (TRST) is used to initialize the H-UDI asynchronously. If no signal is input,
TRST is fixed at 1 by internal pull-up.
Rev.2.0, 07/03, page 620 of 960