SH7055S Datasheet, PDF (559/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.1.2 Block Diagram
Figure 16.1 shows a block diagram of the HCAN.
HCAN0
MBI
Message buffer interface
Mailboxes
Message control
Message data
MC0–MC15, MD0–MD15
LAFM
MPI
Microprocessor interface
CPU interface
Control register
Status register
(CDLC)
CAN
Data Link Controller
Bosch CAN 2.0B active
Tx buffer
Rx buffer
HTxD0
HRxD0
HCAN1
MBI
Message buffer interface
Mailboxes
Message control
Message data
MC0–MC15, MD0–MD15
LAFM
MPI
Microprocessor interface
CPU interface
Control register
Status register
(CDLC)
CAN
Data Link Controller
Bosch CAN 2.0B active
Tx buffer
Rx buffer
HTxD1
HRxD1
Figure 16.1 HCAN Block Diagram
Message Buffer Interface (MBI): The MBI, consisting of mailboxes and a local acceptance filter
mask (LAFM), stores CAN transmit/receive messages (identifiers, data, etc.). Transmit messages
are written by the CPU. For receive messages, the data received by the CDLC is stored
automatically.
Microprocessor Interface (MPI): The MPI, consisting of a bus interface, control register, status
register, etc., controls HCAN internal data, statuses, and so forth.
CAN Data Link Controller (CDLC): The CDLC performs transmission and reception of
messages conforming to the Bosch CAN Ver. 2.0B active standard (data frames, remote frames,
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