SH7055S Datasheet, PDF (824/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 22.9 Hardware Protection
Item
FWE-pin protection
Reset/standby
protection
Description
The input of a low-level signal on the
FWE pin clears the FWE bit of FCCS
and the LSI enters a
programming/erasing-protected state.
• A power-on reset (including a power-
on reset by the WDT) and entry to
standby mode initializes the
programming/erasing interface
registers and the LSI enters a
programming/erasing-protected
state.
• Resetting by means of the RES pin
after power is initially supplied will
not make the LSI enter the reset
state unless the RES pin is held low
until oscillation has stabilized. In the
case of a reset during operation,
hold the RES pin low for the RES
pulse width that is specified in the
section on AC characteristics. If the
LSI is reset during programming or
erasure, data in the flash memory is
not guaranteed. In this case,
execute erasure and then execute
programming again.
Function to be Protected
Download
Programming/
Erasure
—
O
O
O
22.6.2 Software Protection
Software protection is set up in any of three ways: by disabling the downloading of on-chip
programs for programming and erasing, by means of a key code, and by the RAM emulation
register (RAMER).
Rev.2.0, 07/03, page 786 of 960