SH7055S Datasheet, PDF (400/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

pins (TI0A to TI0D, TIO1A to TIO1H, TIO2A to TIO2H, TIO3A to TIO3D, TIO4A to TIO4D,
TIO5A to TIO5D).
A free-running counter (TCNT) starts counting up when a setting is made in the timer start register
(TSTR). When an edge is input at an external pin corresponding to ICR or GR, the corresponding
timer status register (TSR) bit is set and the TCNT value is transferred to ICR or GR. Rising-edge,
falling-edge, or both-edge detection can be selected. By making the appropriate setting in the
interrupt enable register (TIER), an interrupt request can be sent to the CPU.
An example of input capture operation is shown in figure 11.16.
In the example in figure 11.16, channel 1 is activated, and input capture operation is performed
with both-edge detection specified for TIO1A, rising-edge detection for TIO1B, and falling-edge
detection for TIO1C.
Pø
TCNT1
Clock
TCNT1 0000
0001
0002
0003
0004
0005
5678
5679
567A
567B
567C
567D
567E
TIO1A–1C
GR1A
GR1B
GR1C
TSR1
IMF1A
TSR1
IMF1B
TSR1
IMF1C
0003
0003
Cleared by software
567A
0003
567A
Cleared by software
Figure 11.16 Input Capture Operation
11.3.5 One-Shot Pulse Function
Channel 8 has sixteen down-counters (DCNT8A to DCNT8P) and corresponding external pins
(TO8A to TO8P) which can be used as one-shot pulse output pins.
When a value is set beforehand in DCNT and the corresponding bit in the down-counter start
register (DSTR) is set, DCNT starts counting down, and at the same time 1 is output from the
corresponding external pin. When DCNT reaches H'0000 the down-count stops, the corresponding
bit in the timer status register (TSR) is set, and 0 is output from the external pin. The
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