SH7055S Datasheet, PDF (337/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Timer Interrupt Enable Register 11 (TIER11)
TIER11 controls enabling/disabling of channel 11 input capture, compare-match, and overflow
interrupt requests.
Bit: 15
14
13
12
11
10
9
8
—
—
—
—
—
—
— OVE11
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R/W
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
— IME11B IME11A
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R/W R/W
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Interrupt Enable 11 (OVE11): Enables or disables interrupt requests by
OVF11 in TSR11 when OVF11 is set to 1.
Bit 8: OVE11
0
1
Description
OVI11 interrupt requested by OVF11 is disabled
OVI11 interrupt requested by OVF11 is enabled
(Initial value)
• Bits 7 to 2—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 1—Input Capture/Compare-Match Interrupt Enable 11B (IME11B): Enables or disables
interrupt requests by IMF11B in TSR11 when IMF11B is set to 1.
Bit 1: IME11B
0
1
Description
IMI11B interrupt requested by IMF11B is disabled
IMI11B interrupt requested by IMF11B is enabled
(Initial value)
• Bit 0—Input Capture/Compare-Match Interrupt Enable 11A (IME11A): Enables or disables
interrupt requests by IMF11A in TSR11 when IMF11A is set to 1.
Bit 0: IME11A
0
1
Description
IMI11A interrupt requested by IMF11A is disabled
IMI11A interrupt requested by IMF11A is enabled
(Initial value)
Rev.2.0, 07/03, page 299 of 960