SH7055S Datasheet, PDF (31/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

15.5 Usage Notes ...................................................................................................................... 514
15.5.1 TDR Write and TDRE Flag ................................................................................. 514
15.5.2 Simultaneous Multiple Receive Errors ................................................................ 514
15.5.3 Break Detection and Processing .......................................................................... 515
15.5.4 Sending a Break Signal........................................................................................ 515
15.5.5 Receive Error Flags and Transmitter Operation (Synchronous Mode Only)....... 515
15.5.6 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode ... 515
15.5.7 Constraints on DMAC Use .................................................................................. 516
15.5.8 Cautions on Synchronous External Clock Mode ................................................. 517
15.5.9 Caution on Synchronous Internal Clock Mode.................................................... 517
Section 16 Controller Area Network (HCAN) ..................................................519
16.1 Overview........................................................................................................................... 519
16.1.1 Features................................................................................................................ 519
16.1.2 Block Diagram ..................................................................................................... 521
16.1.3 Pin Configuration................................................................................................. 522
16.1.4 Register Configuration......................................................................................... 523
16.2 Register Descriptions ........................................................................................................ 527
16.2.1 Master Control Register (MCR)........................................................................... 527
16.2.2 General Status Register (GSR)............................................................................. 528
16.2.3 Bit Configuration Register (BCR) ....................................................................... 529
16.2.4 Mailbox Configuration Register (MBCR) ........................................................... 533
16.2.5 Transmit Wait Register (TXPR) .......................................................................... 533
16.2.6 Transmit Wait Cancel Register (TXCR) .............................................................. 534
16.2.7 Transmit Acknowledge Register (TXACK) ........................................................ 535
16.2.8 Abort Acknowledge Register (ABACK) ............................................................. 536
16.2.9 Receive Complete Register (RXPR) .................................................................... 537
16.2.10 Remote Request Register (RFPR)........................................................................ 538
16.2.11 Interrupt Register (IRR) ....................................................................................... 538
16.2.12 Mailbox Interrupt Mask Register (MBIMR)........................................................ 542
16.2.13 Interrupt Mask Register (IMR) ............................................................................ 543
16.2.14 Receive Error Counter (REC) .............................................................................. 545
16.2.15 Transmit Error Counter (TEC)............................................................................. 546
16.2.16 Unread Message Status Register (UMSR) ........................................................... 546
16.2.17 Local Acceptance Filter Masks (LAFML, LAFMH)........................................... 547
16.2.18 Message Control (MC0 to MC15) ....................................................................... 549
16.2.19 Message Data (MD0 to MD15) ........................................................................... 552
16.3 Operation .......................................................................................................................... 554
16.3.1 Hardware Reset and Software Reset .................................................................... 554
16.3.2 Initialization after a Hardware Reset.................................................................... 557
16.3.3 Transmit Mode..................................................................................................... 561
16.3.4 Receive Mode ...................................................................................................... 567
16.3.5 HCAN Sleep Mode .............................................................................................. 573
Rev.2.0, 07/03, page xxxi of xxxviii