SH7055S Datasheet, PDF (127/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

6.5 Exceptions Triggered by Instructions
6.5.1 Types of Exceptions Triggered by Instructions
Exception processing can be triggered by trap instructions, general illegal instructions, and illegal
slot instructions, and floating-point instructions, as shown in table 6.9.
Table 6.9 Types of Exceptions Triggered by Instructions
Type
Source Instruction
Trap instructions TRAPA
Illegal slot
instructions
Undefined code placed
immediately after a delayed
branch instruction (delay slot)
and instructions that rewrite
the PC
General illegal
instructions
Floating-point
instructions
Undefined code anywhere
besides in a delay slot
Instruction causing an invalid
operation exception defined in
the IEEE754 standard or a
division-by-zero exception
Comment
Delayed branch instructions: JMP, JSR,
BRA, BSR, RTS, RTE, BF/S, BT/S, BSRF,
BRAF
Instructions that rewrite the PC: JMP, JSR,
BRA, BSR, RTS, RTE, BT, BF, TRAPA,
BF/S, BT/S, BSRF, BRAF
FADD, FSUB, FMUL, FDIV, FMAC,
FCMP/EQ, FCMP/GT, FNEG, FABS, FTRC
6.5.2 Trap Instructions
When a TRAPA instruction is executed, trap instruction exception processing starts up. The CPU
operates as follows:
1. The status register (SR) is saved to the stack.
2. The program counter (PC) is saved to the stack. The PC value saved is the start address of the
instruction to be executed after the TRAPA instruction.
3. The exception service routine start address is fetched from the exception processing vector
table that corresponds to the vector number specified in the TRAPA instruction. That address
is jumped to and the program starts executing. The jump that occurs is not a delayed branch.
Rev.2.0, 07/03, page 89 of 960