SH7055S Datasheet, PDF (397/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Prescaler: The ATU-II has a dedicated prescaler with a 2-stage configuration. The first stage
comprises 5-bit prescalers (PSCR1 to PSCR4) that generate a 1/m clock (where m = 1 to 32) with
respect to clock Pφ. The second prescaler stage allows selection of a clock obtained by further
scaling the clock from the first stage by 2n (where n = 0 to 5) according to the timer control
registers for the respective channels (TCR1A, TCR1B, TCR2A, TCR2B, TCR3 to TCR5, TCR6A,
TCR6B, TCR7A, TCR7B, TCR8, TCR11).
The prescalers of channels 1 to 8 and 11 have a 2-stage configuration, while the channel 0 and 10
prescalers only have a first stage. The first-stage prescaler is common to channels 0 to 5, 8, and
11, and it is not possible to set different first-stage division ratios for each. Channels 6, 7, and 10
each have a first-stage prescaler, and different first-stage division ratios can be set for each.
11.3.2 Free-Running Counter Operation and Cyclic Counter Operation
The free-running counters (TCNT) in ATU-II channels 0 to 5 and 11 start counting up as free-
running counters when the corresponding timer start register (TSTR) bit is set to 1. When TCNT
overflows (channel 0: from H'FFFFFFFF to H'00000000; channels 1 to 5 and 11: from H'FFFF to
H'0000), the OVF bit in the timer status register (TSR) is set to 1. If the OVE bit in the
corresponding timer interrupt enable register (TIER) is set to 1 at this time, an interrupt request is
sent to the CPU. After overflowing, TCNT starts counting up again from H'00000000 or H'0000.
If the TSTR value is cleared to 0 during TCNT operation, the corresponding TCNT halts. In this
case, TCNT is not reset. If external output is being performed from the GR for the corresponding
TCNT, the output value does not change.
Channel 0 free-running counter operation is shown in figure 11.13.
Pø
TSTR
TST0
TCNT0
Clock
TCNT0
TSR0
OVF0
00000001
00000001 00000002 00000003 00000004 00000005 FFFFFFFD FFFFFFFE FFFFFFFF 00000000 00000001 00000002
Cleared by software
Figure 11.13 Free-Running Counter Operation and Overflow Timing
The free-running counters (TCNT) in ATU-II channels 6 and 7 perform cyclic count operations
unconditionally. With channel 3 to 5 free-running counters (TCNT), when the corresponding
T3PWM to T5PWM bit in the timer mode register (TMDR) is set to 1, or the corresponding CCI
bit in the timer I/O control register (TIOR) is set to 1 when bits T3PWM to T5PWM are 0, the
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