SH7055S Datasheet, PDF (294/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 0—Input Capture/Compare-Match Flag 1A (IMF1A): Status flag that indicates GR1A
input capture or compare-match.
Bit 0: IMF1A
0
1
Description
[Clearing condition]
(Initial value)
When IMF1A is read while set to 1, then 0 is written to IMF1A
[Setting conditions]
• When the TCNT1A value is transferred to GR1A by an input capture
signal while GR1A is functioning as an input capture register
• When TCNT1A = GR1A while GR1A is functioning as an output compare
register
TSR1B: TSR1B indicates the status of channel 1 compare-match and overflow.
Bit: 15
14
13
12
11
10
9
—
—
—
—
—
—
—
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
OVF1B
0
R/(W)*
Bit: 7
6
5
4
3
2
1
0
—
—
—
—
—
—
— CMF1
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/(W)*
Note: * Only 0 can be written, to clear the flag.
• Bits 15 to 9—Reserved: These bits are always read as 0. The write value should always be 0.
• Bit 8—Overflow Flag 1B (OVF1B): Status flag that indicates TCNT1B overflow.
Bit 8: OVF1B
0
1
Description
[Clearing condition]
(Initial value)
When OVF1B is read while set to 1, then 0 is written to OVF1B
[Setting condition]
When the TCNT1B value overflows (from H'FFFF to H'0000)
Rev.2.0, 07/03, page 256 of 960