SH7055S Datasheet, PDF (326/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 1—Compare-Match Interrupt Enable 2B (CME2BB): Enables or disables interrupt requests
by CMF2B in TSR2B when CMF2B is set to 1.
Bit 1: CME2B
0
1
Description
CMI2B interrupt requested by CMF2B is disabled
CMI2B interrupt requested by CMF2B is enabled
(Initial value)
• Bit 0—Compare-Match Interrupt Enable 2A (CME2A): Enables or disables interrupt requests
by CMF2A in TSR2B when CMF2A is set to 1.
Bit 0: CME2A
0
1
Description
CMI2A interrupt requested by CMF2A is disabled
CMI2A interrupt requested by CMF2A is enabled
(Initial value)
Timer Interrupt Enable Register 3 (TIER3)
TIER3 controls enabling/disabling of channel 3 to 5 input capture, compare-match, and overflow
interrupt requests.
Bit: 15
—
Initial value: 0
R/W: R
14
OVE5
0
R/W
13
IME5D
0
R/W
12
IME5C
0
R/W
11
IME5B
0
R/W
10
IME5A
0
R/W
9
OVE4
0
R/W
8
IME4D
0
R/W
Bit:
Initial value:
R/W:
7
IME4C
0
R/W
6
IME4B
0
R/W
5
IME4A
0
R/W
4
OVE3
0
R/W
3
IME3D
0
R/W
2
IME3C
0
R/W
1
IME3B
0
R/W
0
IME3A
0
R/W
• Bit 15—Reserved: This bit is always read as 0. The write value should always be 0.
• Bit 14—Overflow Interrupt Enable 5 (OVE5): Enables or disables interrupt requests by OVF5
in TSR3 when OVF5 is set to 1.
Bit 14: OVE5
0
1
Description
OVI5 interrupt requested by OVF5 is disabled
OVI5 interrupt requested by OVF5 is enabled
(Initial value)
Rev.2.0, 07/03, page 288 of 960