SH7055S Datasheet, PDF (699/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

20.3.8 Port D IO Register (PDIOR)
Bit: 15
—
Initial value: 0
R/W: R
14
13
12
11
10
9
8
—
PD13 PD12 PD11 PD10 PD9
PC8
IOR
IOR
IOR
IOR
IOR
IOR
0
0
0
0
0
0
0
R
R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port D IO register (PDIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 14 pins in port D. Bits PD13IOR to PD0IOR correspond to pins
PD13/PULS6/HTxD0/HTxD1 to PD0/TIO1A. PDIOR is enabled when port D pins function as
general input/output pins (PD13 to PD0) or timer input/output pins, and disabled otherwise.
When port D pins function as PD13 to PD0 or timer input/output pins, a pin becomes an output
when the corresponding bit in PDIOR is set to 1, and an input when the bit is cleared to 0.
PDIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
20.3.9 Port D Control Registers H and L (PDCRH, PDCRL)
Port D control registers H and L (PDCRH, PDCRL) are 16-bit readable/writable registers that
select the functions of the 14 multiplex pins in port D. PDCRH selects the functions of the pins for
the upper 6 bits of port D, and PDCRL selects the functions of the pins for the lower 8 bits.
PDCRH and PDCRL are initialized to H'0000 by a power-on reset (excluding a WDT power-on
reset), and in hardware standby mode. They are not initialized in software standby mode or sleep
mode.
Rev.2.0, 07/03, page 661 of 960