SH7055S Datasheet, PDF (372/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.21 Offset Base Registers (OSBR)
The offset base registers (OSBR) are 16-bit registers. The ATU-II has two OSBR registers, one
each in channels 1 and 2.
Channel
1
2
Abbreviation
OSBR1
OSBR2
Function
Dedicated input capture registers with signal from channel 0
ICR0A as input trigger
Offset Base Registers 1 and 2 (OSBR1, OSBR2)
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Initial value: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
OSBR1 and OSBR2 are 16-bit read-only registers used exclusively for input capture. OSBR1 and
OSBR2 use the channel 0 ICR0A input capture register input as their trigger signal, and store the
TCNT1A or TCNT2A value on detection of an edge.
The OSBR registers can only be accessed by a word read.
The OSBR registers are initialized to H'0000 by a power-on reset, and in hardware standby mode
and software standby mode.
For details, see sections 11.3.8, Twin Capture Function.
11.2.22 Cycle Registers (CYLR)
The cycle registers (CYLR) are 16-bit registers. The ATU-II has eight cycle registers, four each in
channels 6 and 7.
Channel
6
7
Abbreviation
CYLR6A–
CYLR6D
CYLR7A–
CYLR7D
Function
16-bit PWM cycle registers
Rev.2.0, 07/03, page 334 of 960