SH7055S Datasheet, PDF (724/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

20.3.18 Port J IO Register (PJIOR)
Bit: 15
14
13
12
11
10
9
8
PJ15 PJ14 PJ13 PJ12 PJ11 PJ10 PJ9
PJ8
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
IOR
IOR
IOR
IOR
IOR
IOR
IOR
IOR
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
The port J IO register (PJIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 16 pins in port J. Bits PJ15IOR to PJ0IOR correspond to pins PJ15/TI9F to
PJ0/TIO2A. PJIOR is enabled when port J pins function as general input/output pins (PJ15 to PJ0)
or ATU-II input/output pins, and disabled otherwise. When ATU-II event counter input is
selected, however, the bits 10 to 15 of the PJIOR should be cleared to 0.
When port J pins function as PJ15 to PJ0 or ATU-II input/output pins, a pin becomes an output
when the corresponding bit in PJIOR is set to 1, and an input when the bit is cleared to 0.
PJIOR is initialized to H'0000 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Rev.2.0, 07/03, page 686 of 960