SH7055S Datasheet, PDF (474/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

13.2.3 Reset Control/Status Register (RSTCSR)
RSTCSR is an 8-bit readable/writable register. (RSTCSR differs from other registers in that it is
more difficult to write. See section 13.2.4, Register Access, for details.) It controls output of the
internal reset signal generated by timer counter (TCNT) overflow. RSTCR is initialized to H'1F by
input of a reset signal from the RES pin, but is not initialized by the internal reset signal generated
by overflow of the WDT. It is initialized to H'1F in hardware standby mode and software standby
mode.
Bit: 7
6
5
4
3
2
1
0
WOVF RSTE RSTS
—
—
—
—
—
Initial value: 0
0
0
1
1
1
1
1
R/W: R/(W)* R/W R/W
R
R
R
R
R
Note: * Only 0 can be written to bit 7 to clear the flag.
• Bit 7—Watchdog Timer Overflow Flag (WOVF): Indicates that TCNT has overflowed (H'FF
to H'00) in watchdog timer mode. This flag is not set in interval timer mode.
Bit 7: WOVF
0
1
Description
No TCNT overflow in watchdog timer mode
[Clearing condition]
When 0 is written to WOVF after reading WOVF
Set by TCNT overflow in watchdog timer mode
(Initial value)
• Bit 6—Reset Enable (RSTE): Selects whether to reset the chip internally if TCNT overflows in
watchdog timer mode.
Bit 6: RSTE
0
1
Description
Not reset when TCNT overflows
(Initial value)
LSI not reset internally, but TCNT and TCSR reset within WDT.
Reset when TCNT overflows
• Bit 5—Reset Select (RSTS): Selects the kind of internal reset to be generated when TCNT
overflows in watchdog timer mode.
Bit 5: RSTS
0
1
Description
Power-on reset
Manual reset
(Initial value)
• Bits 4 to 0—Reserved: These bits are always read as 1. The write value should always be 1.
Rev.2.0, 07/03, page 436 of 960