SH7055S Datasheet, PDF (569/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

HCAN bit rate calculation:
Bit rate [b/s] =
f_CLK
2 × (BRP + 1) × (3 + TSEG1 + TSEG2)
Note: f_CLK = Pφ (peripheral clock (φ/2))
The BCR values are used for BRP, TSEG1, and TSEG2.
BCR Setting Constraints
TSEG1 > TSEG2 = SJW
(SJW = 1 to 4)
3 + TSEG1 + TSEG2 = 8 to 25 time quanta
TSEG2 > B'001 (BRP = B'000000)
TSEG2 > B'000 (BRP > B'000000)
These constraints allow the setting range shown in table 16.4 for TSEG1 and TSEG2 in BCR.
Table 16.4 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR [14:12])
001 010 011 100 101 110 111
TSEG1
0011 No
Yes
No
No
No
No
No
(BCR [11:8]) _{0100 Yes* Yes}
Yes
No
No
No
No
0101 Yes* Yes Yes Yes
No
No
No
0110 Yes* Yes
Yes
Yes
Yes
No
No
0111 Yes* Yes
Yes
Yes
Yes Yes
No
1000 Yes* Yes Yes Yes Yes Yes Yes
1001 Yes* Yes Yes Yes Yes Yes Yes
1010 Yes* Yes Yes Yes Yes Yes Yes
1011 Yes* Yes Yes Yes Yes Yes Yes
1100 Yes* Yes Yes Yes Yes Yes Yes
1101 Yes* Yes Yes Yes Yes Yes Yes
1110 Yes* Yes Yes Yes Yes Yes Yes
1111 Yes* Yes Yes Yes Yes Yes Yes
Notes: The time quanta value for TSEG1 and TSEG2 is the TSEG value + 1.
* Setting is enabled except when BRP[13:8] = B'000000.
Rev.2.0, 07/03, page 531 of 960