SH7055S Datasheet, PDF (506/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE setting is used only in asynchronous mode, and only if the multiprocessor mode bit
(MP) in the serial mode register (SMR) is set to 1 during reception. The MPIE setting is
ignored in synchronous mode or when the MP bit is cleared to 0.
Bit 3: MPIE
0
1
Description
Multiprocessor interrupts are disabled (normal receive operation)
(Initial value)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
Multiprocessor interrupts are enabled. Receive-data-full interrupt
requests (RXI), receive-error interrupt requests (ERI), and setting of the
RDRF, FER, and ORER status flags in the serial status register (SSR)
are disabled until data with the multiprocessor bit set to 1 is received.
The SCI does not transfer receive data from RSR to RDR, does not
detect receive errors, and does not set the RDRF, FER, and ORER
flags in the serial status register (SSR). When it receives data that
includes MPB = 1, MPB is set to 1, and the SCI automatically clears
MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in
SCR are set to 1), and allows the FER and ORER bits to be set.
• Bit 2—Transmit-End Interrupt Enable (TEIE): Enables or disables the transmit-end interrupt
(TEI) requested if TDR does not contain valid transmit data when the MSB is transmitted.
Bit 2: TEIE
Description
0
Transmit-end interrupt (TEI) requests are disabled*
(Initial value)
1
Transmit-end interrupt (TEI) requests are enabled*
Note: * The TEI request can be cleared by reading the TDRE bit in the serial status register (SSR)
after it has been set to 1, then clearing TDRE to 0 and clearing the transmit end (TEND) bit
to 0; or by clearing the TEIE bit to 0.
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