SH7055S Datasheet, PDF (424/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.5 CPU Interface
11.5.1 Registers Requiring 32-Bit Access
Free-running counters 0 and 10A (TCNT0, TCNT10A), input capture registers 0A to 0D and 10A
(ICR0A to ICR0D, ICR10A), and output compare register 10A (OCR10A) are 32-bit registers. As
these registers are connected to the CPU via an internal 16-bit data bus, a read or write (read only,
in the case of ICR0A to ICR0D and ICR10A) is automatically divided into two 16-bit accesses.
Figure 11.44 shows a read from TCNT0, and figure 11.45 a write to TCNT0.
When reading TCNT0, in the first read the TCNT0H (upper 16-bit) value is output to the internal
data bus, and at the same time, the TCNT0L (lower 16-bit) value is output to an internal buffer
register. Then, in the second read, the TCNT0L (lower 16-bit) value held in the internal buffer
register is output to the internal data bus.
When writing to TCNT0, in the first write the upper 16 bits are output to an internal buffer
register. Then, in the second write, the lower 16 bits are output to TCNT0L, and at the same time,
the upper 16 bits held in the internal buffer register are output to TCNT0H to complete the write.
The above method performs simultaneous reading and simultaneous writing of 32-bit data,
preventing contention with an up-count.
Internal data bus
H
CPU
Bus
interface
1st read operation
Module data bus H
L
Internal
buffer register
Module data
bus
TCNT0H
TCNT0L
Internal data bus
L
CPU
Bus
interface
2nd read operation
Module data
bus
L _Internal
buffer register
Figure 11.44 Read from TCNT0
TCNT0H
TCNT0L
Rev.2.0, 07/03, page 386 of 960