SH7055S Datasheet, PDF (546/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Receiving Serial Data (Synchronous Mode): Figures 15.21 and 15.22 show a sample flowchart
for receiving serial data. When switching from asynchronous mode to synchronous mode, make
sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not
be set and both transmitting and receiving will be disabled.
The procedure for receiving serial data is as follows (the steps correspond to the numbers in the
flowchart):
1. SCI initialization: Set the RxD pin using the PFC.
2. Receive error handling: If a receive error occurs, read the ORER bit in SSR to identify the
error. After executing the necessary error handling, clear ORER to 0. Transmitting/receiving
cannot resume if ORER remains set to 1.
3. SCI status check and receive data read: Read the serial status register (SSR), check that RDRF
is set to 1, then read receive data from the receive data register (RDR) and clear RDRF to 0.
The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1.
4. Continue receiving serial data: Read RDR, and clear RDRF to 0 before the MSB (bit 7) of the
current frame is received. If the DMAC is started by a receive-data-full interrupt (RXI) to read
RDR, the RDRF bit is cleared automatically so this step is unnecessary.
Rev.2.0, 07/03, page 508 of 960