SH7055S Datasheet, PDF (656/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

18.1.2 Block Diagram
Figure 18.1 shows a block diagram of the H-UDI.
TCK
TMS
TAP
controller
Internal
bus
controller
H-UDI
interrupt
signal
TDI
Decoder
SDBPR
SDIR
SDSR
SDDRH
16
SDDRL
TDO
Mux
SDIR: Instruction register
SDSR: Status register
SDDRH: Data register H
SDDRL: Data register L
SDBPR: Bypass register
TCK: Test clock
TMS: Test mode select
: Test reset
TDI: Test data input
TDO: Test data output
Figure 18.1 H-UDI Block Diagram
Rev.2.0, 07/03, page 618 of 960