SH7055S Datasheet, PDF (427/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Internal data bus
H
CPU
Bus
interface
1st write operation
H
Module data
bus
TSTR2
TSTR1
TSTR3
Internal data bus
L
CPU
Bus
interface
2nd write operation
L
Module data bus
Figure 11.47 Write to TSTR1, TSTR2, and TSTR3
TSTR2
TSTR1
TSTR3
11.5.3 Registers Requiring 16-Bit Access
The free-running counters (TCNT; but excluding TCNT0, TCNT10A, TCNT10B, TCNT10D, and
TCNT10H), the general registers (GR; but excluding GR9A to GR9D), down-counters (DCNT),
offset base register (OSBR), cycle registers (CYLR), buffer registers (BFR), duty registers (DTR),
timer connection register (TCNR), one-shot pulse terminate register (OTR), down-count start
register (DSTR), output compare registers (OCR: but excluding OCR10B), reload registers
(RLDR8, RLD10C), correction counter clear register (TCCLR10), timer interrupt enable register
(TIER), and timer status register (TSR) are 16-bit registers. These registers are connected to the
CPU via an internal 16-bit data bus, and can be read or written (read only, in the case of OSBR) a
word at a time.
Figure 11.48 shows the operation when performing a word read or write access to TCNT1A.
CPU
Internal data bus
Bus
interface
Module data bus
Figure 11.48 TCNT1A Read/Write Operation
TCNT1A
Rev.2.0, 07/03, page 389 of 960