SH7055S Datasheet, PDF (580/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 0—Mailbox Empty Interrupt Flag (IRR8): Status flag indicating that the next transmit
message can be stored in the mailbox.
Bit 0: IRR8
0
1
Description
[Clearing condition]
Writing 1
(Initial value)
Transmit message has been transmitted or aborted, and new message can
be stored
[Setting condition]
When TXPR (transmit wait register) is cleared by completion of transmission
or completion of transmission abort
16.2.12 Mailbox Interrupt Mask Register (MBIMR)
The mailbox interrupt mask register (MBIMR) is a 16-bit readable/writable register containing
flags that enable or disable individual mailbox (buffer) interrupt requests.
Bit: 15
14
13
12
11
10
9
8
MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 0—Mailbox Interrupt Mask (MBIMR7 to 0, MBIMR15 to 8): Flags that enable or
disable individual mailbox interrupt requests.
Bit x: MBIMRx
0
1
Description
[Transmitting]
Interrupt request to CPU due to TXPR clearing
[Receiving]
Interrupt request to CPU due to RXPR setting
Interrupt requests to CPU disabled
(Initial value)
Rev.2.0, 07/03, page 542 of 960