SH7055S Datasheet, PDF (581/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.2.13 Interrupt Mask Register (IMR)
The interrupt mask register (IMR) is a 16-bit readable/writable register containing flags that
enable or disable requests by individual interrupt sources.
Bit: 15
14
13
12
11
10
9
8
IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1
—
Initial value: 1
1
1
1
1
1
1
0
R/W: R/W R/W R/W R/W R/W R/W R/W
—
Bit: 7
6
5
4
3
2
1
0
—
—
— IMR12 —
—
IMR9 IMR8
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R/W
R
R
R/W R/W
• Bit 15—Overload Frame Interrupt Mask (IMR7): Enables or disables overload frame interrupt
requests.
Bit 15: IMR7
0
1
Description
Overload frame interrupt request (OVR) to CPU by IRR7 enabled
Overload frame interrupt request (OVR) to CPU by IRR7 disabled
(Initial value)
• Bit 14—Bus Off Interrupt Mask (IMR6): Enables or disables bus off interrupt requests caused
by the transmit error counter.
Bit 14: IMR6
0
1
Description
Bus off interrupt request (ERS) to CPU by IRR6 enabled
Bus off interrupt request (ERS) to CPU by IRR6 disabled
(Initial value)
• Bit 13—Error Passive Interrupt Mask (IMR5): Enables or disables error passive interrupt
requests caused by the transmit/receive error counter.
Bit 13: IMR5
0
1
Description
Error passive interrupt request (ERS) to CPU by IRR5 enabled
Error passive interrupt request (ERS) to CPU by IRR5 disabled (Initial value)
Rev.2.0, 07/03, page 543 of 960