SH7055S Datasheet, PDF(496/1002 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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SH7055S Datasheet, PDF (496/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

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â¢ Internal or external transmit/receive clock source: baud rate generator (internal) or SCK pin

(external)

â¢ Four types of interrupts: Transmit-data-empty, transmit-end, receive-data-full, and receive-

error interrupts are requested independently. The transmit-data-empty and receive-data-full

interrupts can start the direct memory access controller (DMAC) to transfer data.

â¢ Selection of LSB-first or MSB-first transfer (8-bit length)

This selection is available regardless of the communication mode. (The descriptions in this

section are based on LSB-first transfer.)

15.1.2 Block Diagram

Figure 15.1 shows a block diagram of the SCI.

Module data bus

Internal

data bus

RxD

TxD

SCK

RDR

TDR

SSR

BRR

SCR

RSR

TSR

SMR

SDCR

Baud rate

generator

Transmit/

receive control

Parity

generation

Clock

Parity check

External clock

RSR: Receive shift register

RDR: Receive data register

TSR: Transmit shift register

TDR: Transmit data register

SCI

SMR: Serial mode register

SCR: Serial control register

SSR: Serial status register

BRR: Bit rate register

SDCR: Serial direction control register

Figure 15.1 SCI Block Diagram

Rev.2.0, 07/03, page 458 of 960

PÏ

PÏ/4

PÏ/16

PÏ/64

TEI

TXI

RXI

ERI

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