SH7055S Datasheet, PDF (342/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 3—Interval Interrupt Bit 13A/13B (ITVE13A/ITVE13B): INTC interval interrupt setting
bit corresponding to bit 13 in TCNT0. The rise of bit 13 in TCNT0 is ANDed with ITVE13x,
the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU.
Bit 3: ITVE13x
0
1
x = A or B
Description
Interrupt request (ITV2x) by rise of TCNT0 bit 13 is disabled
Interrupt request (ITV2x) by rise of TCNT0 bit 13 is enabled
(Initial value)
• Bit 2—Interval Interrupt Bit 12A/12B (ITVE12A/ITVE12B): INTC interval interrupt setting
bit corresponding to bit 12 in TCNT0. The rise of bit 12 in TCNT0 is ANDed with ITVE12x,
the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU.
Bit 2: ITVE12x
0
1
x = A or B
Description
Interrupt request (ITV2x) by rise of TCNT0 bit 12 is disabled
Interrupt request (ITV2x) by rise of TCNT0 bit 12 is enabled
(Initial value)
• Bit 1—Interval Interrupt Bit 11A/11B (ITVE11A/ITVE11B): INTC interval interrupt setting
bit corresponding to bit 11 in TCNT0. The rise of bit 11 in TCNT0 is ANDed with ITVE11x,
the result is stored in IIF2x in TSR0, and an interrupt request is sent to the CPU.
Bit 1: ITVE11x
0
1
x = A or B
Description
Interrupt request (ITV2x) by rise of TCNT0 bit 11 is disabled
Interrupt request (ITV2x) by rise of TCNT0 bit 11 is enabled
(Initial value)
• Bit 0—Interval Interrupt Bit 10 (ITVE10): INTC interval interrupt setting bit corresponding to
bit 10 in TCNT0. The rise of bit 10 in TCNT0 is ANDed with ITVE10x, the result is stored in
IIF2x in TSR0, and an interrupt request is sent to the CPU.
Bit 0: ITVE10x
Description
0
Interrupt request (ITV2x) by rise of TCNT0 bit 10 is disabled (Initial value)
1
Interrupt request (ITV2x) by rise of TCNT0 bit 10 is enabled
x = A or B
For details, see section 11.3.7, Interval Timer Operation.
Rev.2.0, 07/03, page 304 of 960