SH7055S Datasheet, PDF (472/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

13.2.2 Timer Control/Status Register (TCSR)
The timer control/status register (TCSR) is an 8-bit readable/writable register. (TCSR differs from
other registers in that it is more difficult to write to. See section 13.2.4, Register Access, for
details.) TCSR performs selection of the timer counter (TCNT) input clock and mode.
TCSR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Bit: 7
6
5
4
3
2
1
OVF WT/IT TME
—
—
CKS2 CKS1
Initial value: 0
0
0
1
1
0
0
R/W: R/(W)* R/W R/W
R
R
R/W R/W
Note: * The only operation permitted on the OVF bit is a write of 0 after reading 1.
0
CKS0
0
R/W
• Bit 7—Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00 in
interval timer mode. This flag is not set in the watchdog timer mode.
Bit 7: OVF
0
1
Description
No overflow of TCNT in interval timer mode
[Clearing condition]
When 0 is written to OVF after reading OVF
TCNT overflow in interval timer mode
(Initial value)
• Bit 6—Timer Mode Select (WT/IT): Selects whether to use the WDT as a watchdog timer or
interval timer. When TCNT overflows, the WDT either generates an interval timer interrupt
(ITI) or generates a WDTOVF signal, depending on the mode selected.
Bit 6: WT/IT
0
1
Description
Interval timer mode: interval timer interrupt (ITI) request to the CPU
when TCNT overflows
(Initial value)
Watchdog timer mode: WDTOVF signal output externally when TCNT
overflows. (Section 13.2.3, Reset Control/Status Register (RSTCSR),
describes in detail what happens when TCNT overflows in watchdog
timer mode.)
Rev.2.0, 07/03, page 434 of 960