SH7055S Datasheet, PDF (72/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 2.3 Delayed Branch Instructions
SH7055SF CPU
BRA
TRGET
ADD
R1,R0
Description
Executes the ADD before
branching to TRGET.
Example of Conventional CPU
ADD.W R1,R0
BRA
TRGET
Multiply/Multiply-and-Accumulate Operations: 16-bit × 16-bit → 32-bit multiply operations
are executed in one to two cycles. 16-bit × 16-bit + 64-bit → 64-bit multiply-and-accumulate
operations are executed in two to three cycles. 32-bit × 32-bit → 64-bit multiply and 32-bit × 32-
bit + 64bit → 64-bit multiply-and-accumulate operations are executed in two to four cycles.
T Bit: The T bit in the status register changes according to the result of the comparison, and in
turn is the condition (true/false) that determines if the program will branch. The number of
instructions that change the T bit is kept to a minimum to improve the processing speed (table
2.4).
Table 2.4 T Bit
SH7055SF CPU
CMP/GE R1,R0
BT
TRGET0
BF
TRGET1
ADD
CMP/EQ
BT
#1,R0
#0,R0
TRGET
Description
T bit is set when R0 = R1. The
program branches to TRGET0
when R0 = R1 and to TRGET1
when R0 < R1.
T bit is not changed by ADD.
T bit is set when R0 = 0. The
program branches if R0 = 0.
Example of Conventional CPU
CMP.W R1,R0
BGE TRGET0
BLT TRGET1
SUB.W #1,R0
BEQ TRGET
Immediate Data: Byte (8-bit) immediate data resides in the instruction code. Word or longword
immediate data is not input via instruction codes but is stored in a memory table. An immediate
data transfer instruction (MOV) accesses the memory table using the PC relative addressing mode
with displacement (table 2.5).
Rev.2.0, 07/03, page 34 of 960