SH7055S Datasheet, PDF (338/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.2.7 Interval Interrupt Request Registers (ITVRR)
The interval interrupt request registers (ITVRR) are 8-bit registers. The ATU-II has three ITVRR
registers in channel 0.
Channel
0
Abbreviation
ITVRR1
ITVRR2A
ITVRR2B
Function
TCNT0 bit 6 to 9 interval interrupt generation and A/D2 converter
activation
TCNT0 bit 10 to 13 interval interrupt generation and A/D0
converter activation
TCNT0 bit 10 to 13 interval interrupt generation and A/D1
converter activation
Interval Interrupt Request Register 1 (ITVRR1)
Bit:
Initial value:
R/W:
7
ITVA9
0
R/W
6
ITVA8
0
R/W
5
ITVA7
0
R/W
4
ITVA6
0
R/W
3
ITVE9
0
R/W
2
ITVE8
0
R/W
1
ITVE7
0
R/W
0
ITVE6
0
R/W
ITVRR1 is an 8-bit readable/writable register that detects the rise of bits corresponding to the
channel 0 free-running counter (TCNT0) and controls cyclic interrupt output and A/D2 converter
activation.
ITVRR1 is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
• Bit 7—A/D2 Converter Interval Activation Bit 9 (ITVA9): A/D2 converter activation setting
bit corresponding to bit 9 in TCNT0. The rise of bit 9 in TCNT0 is ANDed with ITVA9, and
the result is output to the A/D2 converter as an activation signal.
Bit 7: ITVA9
0
1
Description
A/D2 converter activation by rise of TCNT0 bit 9 is disabled
A/D2 converter activation by rise of TCNT0 bit 9 is enabled
(Initial value)
Rev.2.0, 07/03, page 300 of 960