SH7055S Datasheet, PDF (210/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 10.2 Selecting On-Chip Peripheral Module Request Modes with the RS Bits
DMAC
Transfer
Request DMAC Transfer
RS4 RS3 RS2 RS1 RS0 Source Request Signal
Transfer
Source
Transfer
Destination Bus Mode
0 0 0 0 1 SCI0
TXI0 (SCI0 transmit- Donít care* TDR0
transmit data-empty transfer
block
request)
Burst/cycle-
steal
1 0 SCI0
RXI0 (SCI0 receive- RDR0
receive data-full transfer
block
request)
Donít care* Burst/cycle-
steal
1 SCI1
TXI1 (SCI1 transmit- Donít care* TDR1
transmit data-empty transfer
block
request)
Burst/cycle-
steal
1 0 0 SCI1
RXI1 (SCI1 receive- RDR1
receive data-full transfer
block
request)
Donít care* Burst/cycle-
steal
1 SCI2
TXI2 (SCI2 transmit- Donít care* TDR2
transmit data-empty transfer
block
request)
Burst/cycle-
steal
1 0 SCI2
RXI2 (SCI2 receive- RDR2
receive data-full transfer
block
request)
Donít care* Burst/cycle-
steal
1 SCI3
TXI3 (SCI3 transmit- Donít care* TDR3
transmit data-empty transfer
block
request)
Burst/cycle-
steal
1 0 0 0 SCI3
RXI3 (SCI3 receive- RDR3
receive data-full transfer
block
request)
Donít care* Burst/cycle-
steal
1 SCI4
TXI4 (SCI4 transmit- Donít care* TDR4
transmit data-empty transfer
block
request)
Burst/cycle-
steal
1 0 SCI4
RXI4 (SCI4 receive- RDR4
receive data-full transfer
block
request)
Donít care* Burst/cycle-
steal
1 A/D0
ADI0 (A/D0
conversion end
interrupt)
ADDR0–
ADDR11
Donít care* Burst/cycle-
steal
1 0 0 A/D1
ADI1 (A/D1
conversion end
interrupt)
ADDR12– Donít care* Burst/cycle-
ADDR23
steal
1 A/D2
ADI2 (A/D2
conversion end
interrupt)
ADDR24– Donít care* Burst/cycle-
ADDR31
steal
1 1 HCAN0 RM0 (HCAN0
receive interrupt)
MD0–MD15 Donít care* Burst/cycle-
steal
Rev.2.0, 07/03, page 172 of 960