SH7055S Datasheet, PDF (572/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bits 15 to 9 and 7 to 0—Transmit Wait Register (TXPR7 to 1, TXPR15 to 8): These bits set a
CAN bus arbitration wait for the corresponding mailboxes.
Bit x: TXPRx
0
1
Description
Transmit message idle state in corresponding mailbox
(Initial value)
[Clearing condition]
Message transmission completion and cancellation completion
Transmit message transmit wait in corresponding mailbox (CAN bus
arbitration)
x = 1 to 15
• Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
16.2.6 Transmit Wait Cancel Register (TXCR)
The transmit wait cancel register (TXCR) is a 16-bit readable/writable register that controls
cancellation of transmit wait messages in mailboxes (buffers).
Bit: 15
14
13
12
11
10
9
8
TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1 —
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W
R
Bit: 7
6
5
4
3
2
1
0
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 9 and 7 to 0—Transmit Wait Cancel Register (TXCR7 to 1, TXCR15 to 8): These
bits control cancellation of transmit wait messages in the corresponding HCAN mailboxes.
Bit x: TXCRx
0
1
Description
Transmit message cancellation idle state in corresponding mailbox
(Initial value)
[Clearing condition]
Completion of TXPR clearing (when transmit message is canceled normally)
TXPR cleared for corresponding mailbox (transmit message cancellation)
• Bit 8—Reserved: This bit always reads 0. The write value should always be 0.
Rev.2.0, 07/03, page 534 of 960