SH7055S Datasheet, PDF (159/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

8.1.3 Register Configuration
The UBC has the six registers shown in table 8.1. Break conditions are established using these
registers.
Table 8.1 Register Configuration
Name
Abbr.
Initial
R/W Value Address*
Access
Size
User break address register H
UBARH R/W H'0000 H'FFFFEC00 8, 16, 32
User break address register L
UBARL R/W H'0000 H'FFFFEC02 8, 16, 32
User break address mask register H UBAMRH R/W H'0000 H'FFFFEC04 8, 16, 32
User break address mask register L UBAMRL R/W H'0000 H'FFFFEC06 8, 16, 32
User break bus cycle register
UBBR
R/W H'0000 H'FFFFEC08 8, 16, 32
User break control register
UBCR
R/W H'0000 H'FFFFEC0A 8, 16, 32
Note: * In register access, three cycles are required for byte access and word access, and six
cycles for longword access.
8.2 Register Descriptions
8.2.1 User Break Address Register (UBAR)
UBARH:
Bit:
Initial value:
R/W:
15
UBA31
0
R/W
14
UBA30
0
R/W
13
UBA29
0
R/W
12
UBA28
0
R/W
11
UBA27
0
R/W
10
UBA26
0
R/W
9
UBA25
0
R/W
8
UBA24
0
R/W
Bit:
Initial value:
R/W:
7
UBA23
0
R/W
6
UBA22
0
R/W
5
UBA21
0
R/W
4
UBA20
0
R/W
3
UBA19
0
R/W
2
UBA18
0
R/W
1
UBA17
0
R/W
0
UBA16
0
R/W
Rev.2.0, 07/03, page 121 of 960