SH7055S Datasheet, PDF (575/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

16.2.9 Receive Complete Register (RXPR)
The receive complete register (RXPR) is a 16-bit readable/writable register containing status flags
that indicate normal reception of messages (data frames or remote frames) in mailboxes (buffers).
In the case of remote frame reception, the corresponding bit in the remote request register (RFPR)
is also set.
Bit: 15
14
13
12
11
10
9
8
RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 7
6
5
4
3
2
1
0
RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
• Bits 15 to 0—Receive Complete Register (RXPR7 to 0, RXPR15 to 8): These bits indicate that
a receive message has been received normally in the corresponding mailbox.
Bit x: RXPRx
0
1
Description
[Clearing condition]
Writing 1
(Initial value)
Completion of message (data frame or remote frame) reception in
corresponding mailbox
Rev.2.0, 07/03, page 537 of 960