SH7055S Datasheet, PDF (422/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.4.2 Status Flag Clearing
Clearing by CPU Program: The interrupt status flag is cleared when the CPU writes 0 to the flag
after reading it while set to 1.
The procedure and timing in this case are shown in figure 11.42.
Start
Read 1 from TSR
CK
Address
TSR write cycle
T1
T2
TSR address
Write 0 to TSR
Internal write
signal
Interrupt status
flag cleared
Interrupt status flag
IMF, ICF, CMF,
OVF, OSF, IIF
Interrupt request
signal
Figure 11.42 Procedure and Timing for Clearing by CPU Program
Rev.2.0, 07/03, page 384 of 960