SH7055S Datasheet, PDF (548/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Error handling
Overrun error handling
Clear ORER bit in SSR to 0
End
Figure 15.22 Sample Flowchart for Serial Receiving (2)
Figure 15.23 shows an example of the SCI receive operation.
Transfer direction
Serial clock
Serial
data
Bit 7 Bit 0
Bit 7 Bit 0 Bit 1
Bit 6 Bit 7
RDRF
ORER
RXI interrupt
request
Read data with RXI
interrupt processing
routine and clear
RDRF bit to 0
1 frame
RXI interrupt
request
ERI interrupt
request generated
by overrun error
Figure 15.23 Example of SCI Receive Operation
In receiving, the SCI operates as follows:
1. The SCI synchronizes with serial clock input or output and initializes internally.
2. Receive data is shifted into RSR in order from the LSB to the MSB. After receiving the data,
the SCI checks that RDRF is 0 so that receive data can be loaded from RSR into RDR. If this
check passes, the SCI sets RDRF to 1 and stores the receive data in RDR. If the check does not
pass (receive error), the SCI operates as indicated in table 15.11 and no further transmission or
Rev.2.0, 07/03, page 510 of 960