SH7055S Datasheet, PDF (648/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

17.4.3 Analog Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit in A/D0, A/D1, and A/D2. The A/D
converter samples the analog input at time t_D (A/D conversion start delay time) after the ADST bit
is set to 1, then starts conversion. Figure 17.6 shows the A/D conversion timing.
The A/D conversion time (t_CONV) includes t_D and the analog input sampling time (t_SPL). The length of
t_D is not fixed, since it includes the time required for synchronization of the A/D conversion
operation. The total conversion time therefore varies within the ranges shown in table 17.4.
In scan mode, the t_CONV values given in table 17.4 apply to the first conversion. In the second and
subsequent conversions, t_CONV is fixed at 512 states when CKS = 0 or 256 states when CKS = 1.
Table 17.4 A/D Conversion Time (Single Mode)
Item
A/D conversion start
delay time
Input sampling time
A/D conversion time
Symbol
t
D
CKS = 0:
φ = 20 to 40 MHz
Min Typ Max
20 — 34
t_SPL
t_CONV
— 128 —
518 — 532
CKS = 1:
φ = 20 MHz
Min Typ Max
12 — 18
— 64 —
262 — 268
Unit
States
(φ base)
Rev.2.0, 07/03, page 610 of 960