SH7055S Datasheet, PDF (886/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 24.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral function status in each mode and the procedures for
canceling each mode.
Table 24.1 Power-Down State Conditions
State
Mode
On-Chip
Entering
CPU
Peripheral
Procedure Clock CPU Registers Modules RAM Pins
Canceling
Procedure
Hardware Low-level Halted Halted Halted
standby input at
HSTBY pin
Software
standby
Execute
Halted Halted Held
SLEEP
instruction
with SSBY
bit set to 1 in
SBYCR
Undefined
Held^*2 Initialized High-level input
at HSTBY pin,
executing
power-on reset
Halted^*1
Held
Held or
high
imped-
ance^*3
• NMI
interrupt
• Power-on
reset
Sleep
Execute
Runs Halted Held
Run
SLEEP
instruction
with SSBY
bit cleared to
0 in SBYCR
Held Held
• Interrupt
• DMA
address
error
• Power-on
reset
• Manual
reset
Notes: SBYCR: Standby control register
SSBY: Software standby bit
*1 Some bits within on-chip peripheral module registers are initialized in software standby
mode, and some are not. See table A.2, Register States in Reset and Power-Down
States. Also refer to the register descriptions for each peripheral module.
*2 Clear the RAME bit of the SYSCR to 0 in advance when changing the state from the
program execution state to the hardware standby state.
*3 The state of the I/O ports in standby mode is set by the port high impedance bit (HIZ) in
SBYCR. See section 24.2.1, Standby Control Register (SBYCR). For details of other
pin states, refer to appendix B, Pin States.
Rev.2.0, 07/03, page 848 of 960