SH7055S Datasheet, PDF (239/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

11.1.3 Register Configuration
Table 11.3 summarizes the ATU-II registers.
Table 11.3 ATU-II Registers
Channel Name
Abbrevia-
tion
R/W
Common Timer start register 1 TSTR1 R/W
Timer start register 2 TSTR2 R/W
Timer start register 3 TSTR3 R/W
Prescaler register 1 PSCR1 R/W
Prescaler register 2 PSCR2 R/W
Prescaler register 3 PSCR3 R/W
Prescaler register 4 PSCR4 R/W
0
Free-running counter TCNT0H R/W
0H
Free-running counter TCNT0L R/W
0L
Input capture register ICR0AH R
0AH
Input capture register ICR0AL R
0AL
Input capture register ICR0BH R
0BH
Input capture register ICR0BL R
0BL
Input capture register ICR0CH R
0CH
Input capture register ICR0CL R
0CL
Input capture register ICR0DH R
0DH
Input capture register ICR0DL R
0DL
Timer interval interrupt ITVRR1 R/W
request register 1
Timer interval interrupt ITVRR2A R/W
request register 2A
Initial
Value Address
Access Section
Size (Bits) No.
H'00 H'FFFFF401 8, 16, 32 11.2.1
H'00 H'FFFFF400
H'00 H'FFFFF402
H'00 H'FFFFF404 8
11.2.2
H'00 H'FFFFF406
H'00 H'FFFFF408
H'00 H'FFFFF40A
H'0000 H'FFFFF430 32
11.2.15
H'0000
H'0000 H'FFFFF434
11.2.19
H'0000
H'0000 H'FFFFF438
H'0000
H'0000 H'FFFFF43C
H'0000
H'0000 H'FFFFF420
H'0000
H'00 H'FFFFF424 8
11.2.7
H'00 H'FFFFF426
Rev.2.0, 07/03, page 201 of 960