SH7055S Datasheet, PDF (635/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

17.2.3 A/D Control Registers 0 to 2 (ADCR0 to ADCR2)
A/D control registers 0 to 2 (ADCR0 to ADCR2) are 8-bit readable/writable registers that control
the start of A/D conversion and selects the operating clock for A/D0 to A/D2.
ADCR0 to ADCR2 are initialized to H'0F by a power-on reset, and in hardware standby mode and
software standby mode.
Bits 3 to 0 of ADCR0 to ADCR2 are reserved. These bits cannot be modified. These bits are
always read as 1.
Bit: 7
6
5
4
3
2
1
0
TRGE CKS ADST ADCS —
—
—
—
Initial value: 0
0
0
0
1
1
1
1
R/W: R/W R/W R/W R/W
R
R
R
R
• Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external
input or the ATU-II.
Bit 7:
TRGE
0
1
Description
A/D conversion triggering by external input or ATU-II is disabled
A/D conversion triggering by external input or ATU-II is enabled
(Initial value)
For details of external or ATU-II trigger selection, see section 17.2.5, A/D Trigger Registers 0
to 2 (ADTRGR0 to ADTRGR2).
When ATU triggering is selected, clear bit 7 of registers ADTRGR0 to ADTRGR2 to 0.
When external triggering is selected, upon input of a low level to the ADTRG0 or ADTRG1
pin after TRGE has been set to 1, the A/D converter detects the low level and sets the ADST
bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the
ADST bit by software. External triggering of A/D conversion is only enabled when the ADST
bit is cleared to 0.
When external triggering is used, the low level input to the ADTRG0 or ADTRG1 pin must be
at least 1.5 Pφ clock cycles in width. For details, see section 17.4.4, External Triggering of
A/D Conversion.
Rev.2.0, 07/03, page 597 of 960