SH7055S Datasheet, PDF (892/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

24.3 Hardware Standby Mode
24.3.1 Transition to Hardware Standby Mode
The chip enters hardware standby mode when the HSTBY and RES pins go low. Set the pins
following to mode setup pin shown in section 4, Operating modes. Operation with other pin set up
are not guaranteed.
Hardware standby mode reduces power consumption drastically by halting all SH7055SF
functions. As the transition to hardware standby mode is made by means of external pin input, the
transition is made asynchronously, regardless of the current state of the SH7055SF, and therefore
the chip state prior to the transition is not preserved. However, on-chip RAM data is retained as
long as the specified voltage is supplied. To retain on-chip RAM data, clear the RAM enable bit
(RAME) to 0 in the system control register (SYSCR) before driving the HSTBY pin low. See
appendix B, Pin States, for the pin states in hardware standby mode.
24.3.2 Canceling Hardware Standby Mode
Hardware standby mode is canceled by means of the HSTBY pin and RES pin. When HSTBY is
driven high while RES is low, the clock oscillator starts running. The RES pin should be held low
long enough for clock oscillation to stabilize. When RES is driven high, power-on reset exception
processing is started and a transition is made to the program execution state.
24.3.3 Hardware Standby Mode Timing
Figure 24.2 shows sample pin timings for hardware standby mode. A transition to hardware
standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware
standby mode is canceled by driving HSTBY high, waiting for clock oscillation to stabilize, then
switching RES from low to high.
Rev.2.0, 07/03, page 854 of 960