SH7055S Datasheet, PDF (578/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bit 11—Transmit Overload Warning Interrupt Flag (IRR3): Status flag indicating the error
warning state caused by the transmit error counter.
Bit 11: IRR3
0
1
Description
[Clearing condition]
Writing 1
Error warning state caused by transmit error
[Setting condition]
When TEC ≥ 96
(Initial value)
• Bit 10—Remote Frame Request Interrupt Flag (IRR2): Status flag indicating that a remote
frame has been received in a mailbox.
Bit 10: IRR2
0
1
Description
[Clearing condition]
Clearing of all bits in RFPR (remote request wait register)
Remote frame received and stored in mailbox
[Setting conditions]
When remote frame reception is completed.
When corresponding MBIMR = 0.
(Initial value)
• Bit 9—Receive Message Interrupt Flag (IRR1): Status flag indicating that a mailbox receive
message has been received normally.
Bit 9: IRR1
0
1
Description
[Clearing condition]
Clearing of all bits in RXPR (receive complete register) when MBIMR is 0
(Initial value)
Data frame or remote frame received and stored in mailbox
[Setting conditions]
When data frame or remote frame reception is completed.
When corresponding MBIMR = 0.
Rev.2.0, 07/03, page 540 of 960