SH7055S Datasheet, PDF (660/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

• Bits 15 to 12—Test Instruction Bits (TS3 to TS0): The instruction configuration is shown in
table 18.4.
Table 18.4 Instruction Configuration
TS3
TS2
TS1
TS0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Instruction
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
H-UDI interrupt
Reserved
Reserved
Reserved
Reserved
Bypass mode
(Initial value)
• Bits 11 to 0—Reserved: These bits always read 0. The write value should always be 0.
Rev.2.0, 07/03, page 622 of 960