SH7055S Datasheet, PDF (138/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

7.2.6 Interrupt Exception Vectors and Priority Rankings
Table 7.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. See table 6.4, Calculating Exception Processing Vector Table Addresses,
in section 6, Exception Processing.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A–L (IPRA–IPRL). The ranking of
interrupt sources for IPRC–IPRL, however, must be the order listed under Priority within IPR
Setting Range in table 7.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ
interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or
more interrupt sources and interrupts from those sources occur simultaneously, their priority order
is the default priority order indicated at the right in table 7.3.
Rev.2.0, 07/03, page 100 of 960