SH7055S Datasheet, PDF (143/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

Table 7.3 Interrupt Exception Processing Vectors and Priorities (cont)
Interrupt Source
ATU7
CMI7A
CMI7B
CMI7C
CMI7D
ATU8 ATU81 OSI8A
OSI8B
OSI8C
OSI8D
ATU82 OSI8E
OSI8F
OSI8G
OSI8H
ATU83 OSI8I
OSI8J
OSI8K
OSI8L
Interrupt Vector
Vector Table
Vector Address
No. Offset
Interrupt
Priority
(Initial
Value)
Priority
Corre- within IPR
sponding Setting
IPR (Bits) Range
148 H'00000250 to 0 to 15 (0) IPRG
↑
1
H'00000253
(3–0)
149 H'00000254 to
2
H'00000257
150 H'00000258 to
3
H'0000025B
151 H'0000025C to
H'0000025F
↓
4
152 H'00000260 to 0 to 15 (0) IPRH
↑
1
H'00000263
(15–12)
153 H'00000264 to
2
H'00000267
154 H'00000268 to
3
H'0000026B
155 H'0000026C to
H'0000026F
↓
4
156 H'00000270 to 0 to 15 (0) IPRH
↑
1
H'00000273
(11–8)
157 H'00000274 to
2
H'00000277
158 H'00000278 to
3
H'0000027B
159 H'0000027C to
H'0000027F
↓
4
160 H'00000280 to 0 to 15 (0) IPRH
↑
1
H'00000283
(7–4)
161 H'00000284 to
2
H'00000287
162 H'00000288 to
3
H'0000028B
163 H'0000028C to
H'0000028F
↓
4
Default
Priority
High
Low
Rev.2.0, 07/03, page 105 of 960