SH7055S Datasheet, PDF (216/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

CK
A21–A0
Transfer
source
address (H)
Transfer
source
address (L)
NOP
Indirect
address
Transfer
destination
address
D15–D0
Internal
address
bus
Internal
data bus
DMAC
indirect
address
buffer
DMAC
data
buffer
Indirect
address (H)
Indirect
address (L)
Transfer source
address ∗¹
NOP
Indirect address
∗2
Transfer
data
Transfer
data
Indirect
address
Transfer Transfer
data
data
Indirect
address
Transfer
data
,
Address read cycle
(1st)
(2nd)
NOP
cycle
Data
read cycle
Data
write cycle
(3rd)
(4th)
Notes: ∗1 The internal address bus is controlled by the port and does not change.
∗2 The DMAC does not latch the value until 32-bit data is read from the internal
data bus.
Figure 10.6 Dual Address Mode and Indirect Address Transfer Timing Example 1
External Memory Space → External Memory Space
(External memory space has 16-bit width)
Rev.2.0, 07/03, page 178 of 960