SH7055S Datasheet, PDF (890/1002 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7000 Series

24.2.3 Module Standby Control Register (MSTCR)
Bit: 7
6
5
4
3
2
1
0
—
—
—
— MSTOP3 MSTOP2 MSTOP1 MSTOP0
Initial value: 0
0
0
0
0
0
0
1
R/W: R
R
R
R
R/W
R/W
R/W
R/W
The module standby control register (MSTCR) is an 8-bit readable/writable register that controls
the standby state of the AUD, H-UDI, FPU, and UBC on-chip modules.
MSTCR is initialized to H'01 by a power-on reset.
Note: The method of writing to MSTCR is different from that of ordinary registers to prevent
inadvertent rewriting. See section 24.2.4, Notes on Register Access, for more information.
• Bits 7 to 4—Reserved: These bits always read 0. The write value should always be 0.
• Bit 3—Module Stop 3 (MSTOP3): Specifies halting of the clock supply to the AUD on-chip
peripheral module. Setting the MSTOP3 bit to 1 stops the clock supply to the AUD. To cancel
halting of the clock supply to the AUD, first set the AUD software reset bit (AUDSRST) in the
system control register (SYSCR) to the AUD reset state value. Use of the AUD will then be
enabled by clearing the AUD reset.
Bit 3: MSTOP3
0
1
Description
AUD operates
Clock supply to AUD stopped
(Initial value)
• Bit 2—Module Stop 2 (MSTOP2): Specifies halting of the clock supply to the H-UDI on-chip
peripheral module. Setting the MSTOP2 bit to 1 stops the clock supply to the H-UDI.
Bit 2: MSTOP2
0
1
Description
H-UDI operates
Clock supply to H-UDI stopped
(Initial value)
Rev.2.0, 07/03, page 852 of 960